ADRF6655 CONTROL SOFTWARE
The ADRF6655 can be controlled from most PCs that include
a parallel port output interface. A USB adapter board is also
available from Analog Devices, Inc., to allow for control from
PCs that do not have an accessible parallel port. The USB adapter
evaluation documentation and ordering information can be found
at www.analog.com by searching for EVAL-ADF4XXXZ-USB. The
basic user interfaces are depicted in Figure 66 and Figure 67.
After launching the software, the user is prompted to select a device
from the ADRF product family. Upon selecting the ADRF6655,
the main control interface should appear as shown in Figure 66.
The main control interface allows the user to configure the device
for various modes of operation. The internal synthesizer is
controlled by clicking on any of the numeric values listed in the
RF Section. Attempting to program the REF Input Frequency,
the PFD Frequency, the VCO Frequency [2×LO], or other
values in the RF section launches the Synthesizer Settings—
ADRF6655 Broadband Mixer control module depicted in
Figure 67. From the Synthesizer Settings control interface, the
user can enter the desired Local Oscillator Frequency (MHz),
Channel Step Resolution (kHz), and External Reference
Frequency (MHz). The user can also enable the LO output buffer
and divider options from this menu. After setting the desired
values, it is important to click Upload All Registers and
Windows for the new settings to take effect.
Figure 66. ADRF6655 Software Control Interface
ADRF6655
Figure 67. ADRF6655 Synthesizer Settings User Interface
PLL LOOP FILTER DESIGN
Designing the external loop filter, which connects between the
charge pump output and VCO tuning control pin, is easy with
the help of ADIsimPLL. ADIsimPLL is a free software application
available from Analog Devices for designing PLL loop filters.
Several passive filter topologies are support in ADIsimPLL
along with the necessary component placements on the
evaluation board.
When designing a PLL loop filter, it is important to consider
settling time and phase noise requirements. Figure 68 provides
measured phase noise performance for a typical fast and slow
loop filter design. Note that the wider loop filter offers better
close-in phase noise but degraded phase noise at greater offset
frequencies. The narrow 1.5 kHz loop filter design provides the
best phase noise at 100 kHz and 1 MHz carrier offsets but with
the penalty of decreased frequency settling time and poorer
close-in performance.
0
–20
–40
ADRF6655 1.5kHz LOOP FILTER
–60
LO = 2275MHz
LO = 1100Hz
–80
–100
–120
67kHz LOOP FILTER
–140
–160
–180
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
Figure 68. Phase Noise with Different Loop Filters
100M
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