11.2.26 Mode Bit Reset (FFh)
For Fast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to further reduce
instruction overhead. By setting the Mode Bits (M7-0) to “Ax” hex, the next Fast Read Dual/Quad
I/O operations do not require the BBh/EBh instruction code (See 11.2.10 Fast Read Dual I/O and
11.2.11 Fast Read Quad I/O for detail descriptions).
If the system controller is reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the FM25Q32. However, as with most SPI Serial Flash
memories, the FM25Q32 does not have a hardware Reset pin, so if Mode bits are set to “Ax” hex,
the FM25Q32 will not recognize any standard SPI instruction. To address this possibility, it is
recommended to issue a Mode Bit Reset instruction “FFh” as the first instruction after a system
Reset. Doing so will release the mode Bits for the “Ax” hex state and allow Standard SPI instruction
to be recognized. The Mode Bits Reset instruction is shown in figure 26.
0 1 2 3 4 5 6 7 Mode3
Figure 26. Mode Bits Reset for Fast Read Dual/Quad I/O