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FM25D04C-1ACB2R Просмотр технического описания (PDF) - FIDELIX

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FM25D04C-1ACB2R 32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI FIDELIX
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FM25D04C-1ACB2R Datasheet PDF : 61 Pages
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FM25Q32
11.2.20 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block
Erase operation or a Page Program operation and then read from or program/erase data to, any
other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in figure 20.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h)
are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block
erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is
ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are
not allowed during Program Suspend. Program Suspend is valid only during the Page Program or
Quad Page Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in
the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a
Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the
Suspend instruction will be ignored by the device. A maximum of time of “tSUS” (See AC
Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status
Register will be cleared from 1 to 0 within “tSUS” and the SUS bit in the Status Register will be
set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed
Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier
than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release
the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page,
sector or block that was being suspended may become corrupted. It is recommended for the user
to implement system design techniques against the accidental power interruption and preserve
data integrity during erase/program suspend state.
/CS
Mode 3
CLK
Mode 0
DI
DO
01 23 45 6 7
Instruction (75h)
tSUS
Mode 3
Mode 0
High Impedance
Accept Read or Program
Instruction
Figure 20. Erase Suspend instruction Sequence
preliminary(Aug.18.2010) 36
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