FM25D04C-1ACA6Y View Datasheet(PDF) - FIDELIX

Part Name

Description

Manufacturer

FM25D04C-1ACA6Y

32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI

FIDELIX 

FM25Q32

11.2.19 Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased sate of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and

shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure

19.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase

instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip

Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the

status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when

the cycle is finished and the device is ready to accept other instructions again. After the Chip Erase

cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip

Erase instruction will not be executed if any page is protected by the Block Protect (SEC, TB, BP2,

BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 19. Chip Erase Instruction Sequence Diagram

preliminary(Aug.18.2010) 35

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