FM25D04C-85CA5R View Datasheet(PDF) - FIDELIX
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Manufacturer
FM25D04C-85CA5R Datasheet PDF : 61 Pages
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FM25Q32
11.2.15 Quad Page Program (38h)
The Quad Page Program instruction allows 24-bit address and up to 256 bytes of data to be
programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2 and IO3.
The Quad Page Program can improve performance for PROM Programmer and applications that
have slow clock speed <5MHz. System with faster clock speed will not realize much benefit for the
Quad Page Program instruction since the inherent page program time is much greater than the
time it takes to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1), A Write
Enable instruction must be executed before the device will accept the Quad Page Program
instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then
shifting the instruction code “38h” followed by a 24-bit address (A23-A0) and at least one data, into
the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being
sent to the device. All other functions of Quad Page Program are identical standard Page Program.
The Quad Page Program instruction sequence is shown in figure 15.
/ CS
Mode 3
CLK Mode0
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Instruction(38h)
6 Address Cycle
Byte 1 Byte2 Byte 3 Byte4
20 16 12 8 4 0 4 0 4 0 4 0 4 0
21 17 13 9 5 1 5 1 5 1 5 1 5 1
22 18 14 10 6 2 6 2 6 2 6 2 6 2
23 19 15 11 7 3 7 3 7 3 7 3 7 3
/ CS
CLK
IO0
IO1
IO2
IO3
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Byte 5 Byte6 Byte 7 Byte 8 Byte 9 Byte 10 Byte 11 Byte 12
Mode 3
Mode 0
Byte253 Byte254 Byte255 Byte256
4 0 404040 4 040 40 4 0 404 040 40
5 1 5 15 1 51 51 51 5 1 5 1
6 2 6 26 2 62 62 62 6 2 6 2
51 5151 5 1
62 6262 6 2
73 7 37 3 737 3 73 73 7 3 7 3 7 37 3 73
Figure 15. Quad Page Program Instruction Sequence Diagram
preliminary(Aug.18.2010) 31
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