FM25D04B-85CB4Y View Datasheet(PDF) - FIDELIX

Part Name

Description

Manufacturer

FM25D04B-85CB4Y

32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI

FIDELIX 

FM25Q32

11.2.12 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction

except that address and data bits are input and output through four pins IO0, IO1, IO2, and IO3 and

four Dummy clock are required prior to the data output. The Quad I/O dramatically reduces

instruction overhead allowing faster random access for code executing (XIP) directly from the

Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read

Quad I/O Instruction.

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the

Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The upper nibble of

the Mode (M7-4) controls the length of the next Fast Read Quad I/O instruction through the

instruction or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)

are don’t care (“X”). However, the IO pins should be high-impedance prior to the falling edge of the

first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is

raised and then lowered) does not require the EBh instruction code, as shown in figure 12b. This

reduces the instruction sequence by eight clocks allows the address to be immediately entered

after /CS is asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the next

instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus

retuning normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0) before issuing

normal instructions (See 11.2.25 for detailed descriptions.)

/CS

Mode 3

CLK Mode 0

IO0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instruction(EBh)

40 40 40 4 0

IO Switches from

Input to Output

40 40 4

IO1

51 5 151 51

51 51 5

IO2

62 62 62 6 2

62 62 6

IO3

73 73 73 7 3

73 73 7

A23-16 A15-8 A7-0 M7-0 Dummy Dummy BByyttee13 BBytyet2e4

Figure 12a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

preliminary(Aug.18.2010) 27

Share Link: