FM25D04B-85IA6Y View Datasheet(PDF) - FIDELIX

Part Name

Description

Manufacturer

FM25D04B-85IA6Y

32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI

FIDELIX 

FM25Q32

11.2.11 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining

two IO pins, IO0 and IO1. It is similar to the Fast Read Output (0Bh) instruction but with the

capability to input the Address bits (A23-0) two bits and output data two bits per clock. This

reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in

some applications.

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the

Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 11a. The upper nibble of

the Mode (M7-4) controls the length of the next Fast Read Dual I/O instruction through the

instruction or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)

are don’t care (“X”), However, the IO pins should be high-impedance prior to the falling edge of the

first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Dual I/O instruction (after /CS is raised

and then lowered) does not require the BBh instruction code, as shown in figure 11b. This reduces

the instruction sequence by eight clocks and allows the address to be immediately entered after

/CS is asserted low. If Mode bits (M7-0) are any value other “Ax” hex, the next instruction (after /CS

is raised and then lowered) requires the first byte instruction code, thus returning to normal

operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing

normal instructions (See 11.2.25 for detailed descriptions).

Figure 11a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)

preliminary(Aug.18.2010) 25

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