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FM25D04C-1ACA3T Просмотр технического описания (PDF) - FIDELIX

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FM25D04C-1ACA3T Datasheet PDF : 61 Pages
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11.2.9 Read Data (03h)
The Read Data instruction allows one more data bytes to be sequentially read from the memory.
The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h”
followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The
address is automatically incremented to the next higher address after byte of data is shifted out
allowing for a continuous stream of data. This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in figure 9. If a Read Data instruction is issued while
an Erase, Program or Write Status Register cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle. The Read Data instruction allows clock rates
from D.C to a maximum of fR (see AC Electrical Characteristics).
Mode 3
CLK Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction (03h)
24-Bit Address
23 22 21
High Impedance
Data Out 1
Data Out 2
76 5 43 2 1 07
Figure 9. Read Data Register Instruction Sequence Diagram
preliminary(Aug.18.2010) 23
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