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FM25D04C-1ACA3T Просмотр технического описания (PDF) - FIDELIX

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FM25D04C-1ACA3T 32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI FIDELIX
FIDELIX FIDELIX
FM25D04C-1ACA3T Datasheet PDF : 61 Pages
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FM25Q32
11.2.6 Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status
Register to a 0. The Write Disable instruction in entered by driving /CS low, shifting the instruction
code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase and Chip Erase instructions.
.
/ CS
Mode 3
CLK Mode 0
0 1 2 3 4 5 6 7 Mode 3
Mode 0
Instruction (04 h)
DI
High Impedance
DO
Figure 6. Write Disable Instruction Sequence Diagram
11.2.7 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Register to be read, The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 and “35h”
for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in
figure 7. The Status Register bits are shown in figure 3a and 3b include the BUSY, WEL, BP2-BP0,
TB, SEC, SRP0, SRP1 and QE bits (see description of the Status Register earlier in this
datasheet).
The Status Register instruction may be used at any time, even while a Program, Erase, Write
Security Register or Write Status Register cycle is in progress. This allows the BUSY status bit to
be checked to determine when the cycle is complete and if the device can accept another
instruction. The Status Register can be read continuously, as shown in Figure 7. The instruction is
completed by driving /CS high.
/CS
CLK
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction(05h or 35h)
DI
Status Register out
Status Register out
DO
=MSB
7 65 4 321 07 65 4 321 0 7
Figure 7. Read Status Register Instruction Sequence Diagram
preliminary(Aug.18.2010) 21
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