FM25D04C-85CAWY View Datasheet(PDF) - FIDELIX
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Description
Manufacturer
FM25D04C-85CAWY Datasheet PDF : 61 Pages
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FM25Q32
11.2.4 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status
Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase,
Chip Erase and Write Status Register instruction. The Write Enable instruction is entered by driving
/CS low, shifting the instruction code “06h” into Data Input (DI) pin on the rising edge of CLK, and
then driving /CS high.
/ CS
Mode 3
CLK Mode 0
0 1 2 3 4 5 6 7 Mode 3
Mode 0
Instruction (06 h)
DI
High Impedance
DO
Figure 4. Write Enable Instruction Sequence Diagram
11.2.5 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 12.1 can also be written to as volatile bits.
This gives more flexibility to change the system configuration and memory protection schemes
quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write
Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register
(01h) instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the
Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the
volatile Status Register bit values
/ CS
Mode 3
CLK Mode 0
DI
DO
0 1 2 3 4 5 6 7 Mode 3
Mode 0
Instruction (06 h)
High Impedance
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
preliminary(Aug.18.2010) 20
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