FM25D04B-85IA1Y View Datasheet(PDF) - FIDELIX
Part Name
Description
Manufacturer
FM25D04B-85IA1Y Datasheet PDF : 61 Pages
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FM25Q32
11.1.6 Status Register protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status
register (S8 and S7). The SRP bits control the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0 /WP
0
0
X
0
1
0
0
1
1
1
0
X
1
1
X
Status
Register
Software
Protection
Description
/WP pin no control. The register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
Hardware
Protected
When /WP pin is low the Status Register locked and can not
be written to.
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and
can be written to after a Write Enable instruction, WEL=1
Power Supply Status Register is protected and can not be written to again
Lock-Down
until the next power-down, power-up cycle(1).
One Time
Program
Status Register is permanently protected and can not be
written to.
Note:
1. When SRP1, SRP0=(1,0), a power-down, power-up cycle will change SRP1, SRP0 to(0,0) state.
11.1.7 Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing
an Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program
Resume (7Ah) instruction as well as a power-down, power-up cycle.
11.1.8 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows
Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are
enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING : The QE bit should never be set to a 1 during standard SPI or Dual SPI operation
if the /WP or /HOLD pins are tied directly to the power supply or ground.
preliminary(Aug.18.2010) 14
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