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FM25D04C-1ACB2R Просмотр технического описания (PDF) - FIDELIX

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FM25D04C-1ACB2R 32M-BIT Serial Flash Memory with 4KB Sectors, Dual and QuadI/O SPI FIDELIX
FM25D04C-1ACB2R Datasheet PDF : 61 Pages
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Figure2. Hold condition waveform
Applications that use non-volatile memory must take consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
FM25Q32 provides several means to protect data from inadvertent writes.
10.2.1 Write protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after program and erase
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection until next power-up
One Time Program (OTP) write protection
Upon power-up at power down the FM25Q32 will maintain a reset condition while VCC is below
the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 31). While reset,
all operations are disabled and no instruction is recognized. During power-up and after the VCC
voltage exceeds VWI, instructions related with all program and erase are further disabled for a time
delay of tPUW. This includes the write Enable, Page program, Sector Erase, Block Erase, Chip
Erase, Write Security Register and the Write Status Register instructions. Note that the chip select
pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay
is reached. If needed a pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
program, Sector Erase Chip Erase or Write Status Register and then instructions will be accepted.
After completing a program, erase or write instruction the write Enable (WEL) is automatically
cleared to write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and
setting the Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and BP0) bits.
These setting allow a portion or all the memory to be configured as read only. Used in conjunction
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under
hardware control. See Status Register for further information. Additionally, the Power-down
instruction offers an extra level of write protection as all instructions are ignored except for Release
power-down instruction.
preliminary(Aug.18.2010) 12
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