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M48T35AY-70PC6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T35AY-70PC6 Datasheet PDF : 25 Pages
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M48T35AY, M48T35AV
WRITE Mode
The M48T35AY/V is in the WRITE Mode whenev-
er W and E are low. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid for
tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform
A0-A14
E
W
DQ0-DQ7
tAVEL
tAVAV
VALID
tAVWH
tWHAX
tAVWL
tWLWH
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI00926
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms
A0-A14
E
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
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