49LF002B View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
49LF002B Datasheet PDF : 43 Pages
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2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
Data Sheet
TABLE 9: LPC MEMORY ADDRESS DECODING RANGE FOR SST49LF002B
ID Strapping
Device Access
Address Range
Memory Size
Device #0 - 15
Memory Access
FFFF FFFFH : FFC0 0000H
4 MByte
Register Access
FFBF FFFFH : FF80 0000H
4 MByte
Device #01
Memory Access
000F FFFFH : 000E 0000H
128 KByte
T9.1 1232
1. For device #0 (Boot Device), SST49LF002B decodes the physical addresses of the top 8 blocks (including Boot Block) both at sys-
tem memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
TABLE 10: LPC MEMORY ADDRESS DECODING RANGE FOR SST49LF003B1 AND SST49LF004B
ID Strapping
Device Access
Address Range
Memory Size
Device #0 - 7
Memory Access
FFFF FFFFH : FFC0 0000H
4 MByte
Register Access
FFBF FFFFH : FF80 0000H
4 MByte
Device #8 - 15
Memory Access
FF7F FFFFH : FF40 0000H
4 MByte
Register Access
FF3F FFFFH : FF00 0000H
4 MByte
Device #02
Memory Access
000F FFFFH : 000E 0000H
128 KByte
T10.0 1232
1. For the SST49LF003B, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map).
2. For device #0 (Boot Device), SST49LF003B/004B decodes the physical addresses of the top 2 blocks (including Boot Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
TABLE 11: SST49LF002B LPC MEMORY ADDRESS BITS DEFINITION
A31: A231
1111 1111b or 0000 0000b
A22
1 = Memory Access
0 = Register access
A21: A18
ID[3:0]2
A17:A0
Device Memory address
T11.0 1232
1. For SST49LF002B, the top 8 MByte address range FFFF FFFFH to FF80 0000H and the bottom 128 KByte memory access address
000F FFFFH to 000E 0000H are decoded.
2. See Table 14 for multiple device selection configuration.
TABLE 12: SST49LF003B1 AND SST49LF004B LPC MEMORY ADDRESS BITS DEFINITION
A31: A242
1111 1111b or 0000 0000b
A23
ID[3]3
A22
1 = Memory Access
0 = Register access
A21: A19
ID[2:0]3
A18:A0
Device Memory address
T12.0 1232
1. For the SST49LF003B, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map).
2. For SST49LF003B/004B, the top 16 MByte address range FFFF FFFFH to FF00 0000H and the bottom 128 KByte memory access
address 000F FFFFH to 000E 0000H are decoded.
3. See Table 14 for multiple device selection configuration.
©2005 Silicon Storage Technology, Inc.
19
S71232-05-000
1/05
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