Data Sheet
LPC Memory Read Cycle
2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
TABLE 7: LPC MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents LAD[3:0]
LAD[3:0]1
Direction Comments
1
START
0000
IN
LFRAME# must be active (low) for the device to respond. Only
the last field latched before LFRAME# transitions high will be
recognized. The START field contents (0000b) indicate an LPC
Memory cycle.
2
CYCTYPE
010X
+ DIR
IN
Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
3-10
ADDR
YYYY
IN
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
11
TAR0
1111
IN
In this clock cycle, the host drives the bus to all 1s and then
then Float floats the bus. This is the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float
The SST49LF00xB takes control of the bus during this cycle.
then OUT
13
SYNC
0000
OUT
The SST49LF00xB outputs the value 0000b indicating that it
has received data.
14
DATA
ZZZZ
OUT
ZZZZ is the least-significant nibble of the data byte.
15
DATA
ZZZZ
OUT
ZZZZ is the most-significant nibble of the data byte.
16
TAR0
1111
IN
In this clock cycle, the host drives the bus to all 1s and then
then Float floats the bus. This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float
The SST49LF00xB takes control of the bus during this cycle.
then OUT
1. Field contents are valid on the rising edge of the present clock cycle.
T7.0 1232
LCLK
LFRAME#
LAD[3:0]
CYCTYPE
Start
+
DIR
Address
0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
1 Clock 1 Clock
Load Address in 8 Clocks
A[7:4]
A[3:0]
TAR0 TAR1 Sync
Data
1111b Tri-State 0000b D[3:0] D[7:4]
2 Clocks
1 Clock Data Out 2 Clocks
FIGURE 8: LPC MEMORY READ CYCLE WAVEFORM
TAR
1232 F05.1
©2005 Silicon Storage Technology, Inc.
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