49LF002B View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
Manufacturer
49LF002B Datasheet PDF : 43 Pages
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2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
LPC MODE
Data Sheet
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF00xB supports both single-byte Firmware
Memory Read/Write cycles and single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification, Revision 1.1. The host drives
LFRAME# low for one or more clock cycles to initiate an
LPC cycle. The last latched value of LAD[3:0] before
LFRAME# is the START value. The START value deter-
mines whether the SST49LF00xB will respond to a Firm-
ware Memory Read/Write cycle or a LPC Memory Read/
Write cycle as defined in Table 4.
TABLE 4: FIRMWARE AND LPC MEMORY CYCLES
START FIELD DEFINITION
START
Value Definition
0000
Start of an LPC memory cycle. The direction
(Read or Write) is determined by the second field
of the LPC cycle.
1101 Start of a Firmware Memory Read cycle
1110 Start of a Firmware Memory Write cycle
T4.0 1232
See following sections for details of Firmware Memory and
LPC Memory cycle types. JEDEC standard SDP (Soft-
ware Data Protection) Program and Erase command
sequences are used to initiate Firmware and LPC Memory
Program and Erase operations. See Table 18 for a listing
of Program and Erase commands. Chip-Erase is only
available in PP mode.
©2005 Silicon Storage Technology, Inc.
13
S71232-05-000
1/05
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