ISL12024IRTCZ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
ISL12024IRTCZ Datasheet PDF : 24 Pages
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ISL12024IRTCZ
EEPROM Specifications
PARAMETER
EEPROM Endurance
EEPROM Retention
TEST CONDITIONS
Temperature ≤ +75°C
Serial Interface (I2C) Specifications
DC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
VIL
SDA, and SCL Input Buffer LOW
Voltage
VIH
SDA, and SCL Input Buffer HIGH
Voltage
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage
ILI
Input Leakage Current on SCL
ILO
I/O Leakage Current on SDA
IOL = 4mA
VIN = 5.5V
VIN = 5.5V
MIN
TYP
2,000,000
50
MAX
UNITS
Cycles
Years
MIN
(Note 12)
TYP
-0.3
0.7 x VDD
0.05 x VDD
0
100
100
MAX
(Note 12)
0.3 x VDD
UNITS
V
NOTES
VDD + 0.3
V
V
9, 11
0.4
V
nA
nA
AC Electrical Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 12) TYP (Note 12) UNITS NOTES
fSCL
tIN
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
400
kHz
50
ns
tAA
tBUF
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VDD, until
Data Valid
SDA exits the 30% to 70% of VDD window.
Time the Bus Must be Free Before SDA crossing 70% of VDD during a STOP
the Start of a New Transmission condition, to SDA crossing 70% of VDD during
the following START condition.
1300
900
ns
ns
tLOW Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA START Condition Set-up Time
SCL rising edge to SDA falling edge. Both
600
ns
crossing 70% of VDD.
tHD:STA START Condition Hold Time
From SDA falling edge crossing 30% of VDD to
600
ns
SCL falling edge crossing 70% of VDD.
tSU:DAT Input Data Set-up Time
From SDA exiting the 30% to 70% of VDD
100
ns
window, to SCL rising edge crossing 30% of
VDD.
tHD:DAT Input Data Hold Time
From SCL rising edge crossing 70% of VDD to
0
ns
SDA entering the 30% to 70% of VDD window.
tSU:STO STOP Condition Set-up Time
From SCL rising edge crossing 70% of VDD, to
600
ns
SDA rising edge crossing 30% of VDD.
tHD:STO STOP Condition Hold Time for
From SDA rising edge to SCL falling edge. Both
600
ns
Read, or Volatile Only Write
crossing 70% of VDD.
tDH Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
0
ns
until SDA enters the 30% to 70% of VDD
window.
4
FN6749.0
August 8, 2008
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