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AD9684
DIGITAL OUTPUTS
DIGITAL OUTPUTS
The AD9684 output drivers are for standard ANSI LVDS, but
optionally the drive current can be reduced using Register 0x56A.
The reduced drive current for the LVDS outputs potentially
reduces the digitally induced noise.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
The AD9684 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled when the device is
set for power-down mode.
As shown in Table 24, the function of the output pins changes
based upon the selection of either parallel or byte output mode
in Register 0x568.
Timing
The AD9684 provides latched data with a pipeline delay of
33 input sample clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
Table 23. LVDS Output Configurations
Parallel Output Mode
Number of Virtual
Converters Supported
Parallel Interleaved, Two
2
Converters (0x1)
Parallel Channel Multiplexed, Two 2
Converters (0x3)
Byte Mode, Two Converters (0x5) 2
Byte Mode, Four Converters (0x6) 4
Byte Mode, Eight Converters (0x7) 8
Table 24. Pin Mapping Between LVDS Parallel/Byte Modes
Pin Name
LVDS Parallel Mode Output
DCO−, DCO+
DCO−, DCO+
STATUS−, STATUS+
OVR−, OVR+
D13−, D13+
D13−, D13+
D12−, D12+
D12−, D12+
D11−, D11+
D11−, D11+
D10−, D10+
D10−, D10+
D9−, D9+
D9−, D9+
D8−, D8+
D8−, D8+
D7−, D7+
D7−, D7+
D6−, D6+
D6−, D6+
D5−, D5+
D5−, D5+
D4−, D4+
D4−, D4+
D3−, D3+
D3−, D3+
D2−, D2+
D2−, D2+
D1−, D1+
D1−, D1+
D0−, D0+
D0−, D0+
Minimize the length of the output data lines and the corresponding
loads to reduce transients within the AD9684. These transients
can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9684 is 250 MSPS.
At clock rates below 250 MSPS, dynamic performance may
degrade.
Data Clock Output
The AD9684 also provides a data clock output (DCO) intended
for capturing the data in an external register. The DCO relative
to the data output can be adjusted using Register 0x569.
ADC OVERRANGE
The ADC overrange (OR) indicator is asserted when an overrange
is detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 28 ADC clocks. An overrange at the input is
indicated by the OR bit 28 clock cycles after it occurs.
Virtual Converter
Resolution (Max)
14-bit
14-bit
16-bit
16-bit
16-bit
LVDS Byte Mode Outputs Required
DCO + STATUS + D[13:0]
DCO + STATUS + D[13:7] =
Channel AD[6:0] = Channel B
1 DCO + 1 STATUS + 8 DATA[7:0]
1 DCO + 1 STATUS + 8 DATA[7:0]
1 DCO + 1 STATUS + 8 DATA[7:0]
LVDS Byte Mode Output
DCO−, DCO+
FCO−, FCO+
STATUS−, STATUS+
DATA7−, DATA7+
DATA6−, DATA6+
DATA5−, DATA5+
DATA4−, DATA4+
DATA3−, DATA3+
DATA2−, DATA2+
DATA1−, DATA1+
DATA0−, DATA0+
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
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