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AD9684
Input Common Mode
The analog inputs of the AD9684 are internally biased to the
common mode as shown in Figure 41. The common-mode
buffer has a limited range in that the performance suffers greatly
if the common-mode voltage drops by more than 100 mV.
Therefore, in dc-coupled applications, set the common-mode
voltage to 2.05 V ± 100 mV to ensure proper ADC operation.
Analog Input Controls and SFDR Optimization
The AD9684 offers flexible controls for the analog inputs, such
as input termination and buffer current. All of the available
controls are shown in Figure 41.
AVDD3
VIN+x
10pF
3pF
AVDD3
400Ω
VCM
BUFFER
AVDD3
95
85
4.5×
3.0×
75
2.0×
65
1.5×
55
1.0×
45
35
50 100 150 200 250 300 350 400 450 500
INPUT FREQUENCY (MHz)
Figure 43. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),
10 MHz < fIN < 500 MHz
90
4.5×
5.0×
85
6.0×
7.0×
8.0×
80
VIN–x
3pF
AIN CONTROL
(SPI) REGISTERS
(REG 0x008, REG 0x015,
REG 0x016, REG 0x018,
REG 0x025)
Figure 41. Analog Input Controls (Should the AIN
Using Register 0x018, the buffer currents on each channel can
be scaled to optimize the SFDR over various input frequencies
and bandwidths of interest. As the input buffer currents are set,
the amount of current required by the AVDD3 supply changes.
For a complete list of buffer current settings, see Table 29.
250
230
210
190
170
150
130
110
90
70
50
1.5× 2.5× 3.5× 4.5× 5.5× 6.5× 7.5× 8.5×
BUFFER CURRENT SETTING
Figure 42. AVDD3 Power (IAVDD3) vs. Buffer Current Control Setting in
Register 0x018
75
70
65
500 550 600 650 700 750 800 850 900 950 1000
INPUT FREQUENCY (MHz)
Figure 44. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),
500 MHz < fIN < 1000 MHz
80
75
70
65
60
55
4.5×
5.0×
6.0×
50
7.0×
8.0×
8.0×
45
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
INPUT FREQUENCY (MHz)
Figure 45. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF),
1 GHz < fIN < 2 GHz, Front-End Network Shown in Figure 40
Figure 43, Figure 44, and Figure 45 show how the SFDR can be
optimized using the buffer current setting in Register 0x018 for
different Nyquist zones. At frequencies greater than 1 GHz, it is
better to run the ADC at input amplitudes less than −1 dBFS
(−3 dBFS, for example). This greatly improves the linearity of
the converted signal without sacrificing SNR performance.
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