BR34L02-W View Datasheet(PDF) - ROHM Semiconductor
Part Name
Description
Manufacturer
BR34L02-W Datasheet PDF : 17 Pages
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●AC OPERATING CHARACTERISTICS（Unless otherwise specified Ta=-40～85℃, VCC =1.7～5.5V）
Parameter
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time
*1
SDA and SCL Fall Time
*1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
WP Hold Time
WP Setup Time
WP High Period
FAST-MODE
STANDARD-MODE
Symbol
2.5V≦VCC≦5.5V 1.7V≦VCC≦5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
fSCL
－
－ 400 －
－ 100
kHz
tHIGH
0.6 － － 4.0 － －
μs
tLOW
1.2 － － 4.7 － －
μs
tR
－ － 0.3 － － 1.0
μs
tF
－ － 0.3 － － 0.3
μs
tHD:STA 0.6 － － 4.0 － －
μs
tSU:STA 0.6 － － 4.7 － －
μs
tHD:DAT
0
－－
0
－－
ns
tSU:DAT 50 － － 50 － －
ns
tPD
0.1 － 0.9 0.2 － 3.5
μs
tDH
0.1 － － 0.2 － －
μs
tSU:STO 0.6 － － 4.7 － －
μs
tBUF
1.2 － － 4.7 － －
μs
tWR
－－
5
－－
5
ms
tI
－ － 0.1 － － 0.1
μs
tHD：WP 0
－－
0
－－
ns
tSU：WP 0.1 － － 0.1 － －
μs
tHIGH：WP 1.0 － － 1.0 － －
μs
*1：Not 100％ TESTED
■ABOUT FAST-MODE AND STANDARD-MODE
Fast-mode and Standard-mode is the same operation. So it doesn't mean the different operation. It is only distinguished by
frequency of operation. It defines that the operation up to 100kHz is named "Standard-mode" and the one up to 400kHz is
"Fast-mode".
The value of clock frequency is maximum, it is possible to use the device up to 100kHz in Fast-mode. Lower the power
supply is, more difficult it is to operate in high speed. Under Vcc=2.5V-5.5V, it is operated with 400kHz, Fast-mode (the
same as Standard-mode). Under VCC=1.7V-2.5V, it is only operate with up to 100kHz.
●SYNCHRONOUS DATA TIMING
tR
tF
tHIGH
SCL
SCL
tHD:STA
tSU:DAT tLOW
tHD:DAT
DATA(1)
DATA(n)
SDA
(IN)
tBUF
SDA
(OUT)
tPD
tDH
SDA D1 D0 ACK
WP
ACK
tWR
STOP BIT
Fig.1-(a) SYNCHRONOUS DATA TIMING
○ SDA data is latched into the chip at the rising edge
○ of SCL clock.
○ Output data toggles at the falling edge of SCL clock.
SCL
tSU：WP
ｔＨＤ：WP
Fig.1-(d) WP TIMING OF THE WRITE OPERATION
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
SDA
WP
DATA(1)
D1 D0
ACK
DATA(n)
tHIGH:WP
ACK
START BIT
STOP BIT
Fig.1-(b) START/STOP BIT TIMING
Fig.1-(e) WP TIMING OF THE WRITE CANCEL OPERATION
SCL
SDA
D0 ACK
WRITE DATA(n)
tWR
STOP
CONDITION
START
CONDITION
Fig.1-(c) WRITE CYCLE TIMING
○For the WRITE operation, WP must be "LOW" during the period
of time from the rising edge of the clock which takes in D0 of
first byte until the end of tWR. (See Fig.-1 (d) ) During this
period, WRITE operation is canceled by setting WP "HIGH".
（See Fig.-1 (e)）
○In the case of setting WP "HIGH" during tWR, WRITE operation
is stopped in the middle and the data of accessing address is
not guaranteed. Please write correct data again in the case.
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