RM0008
Memory and bus architecture
In connectivity line devices the main system consists of:
• Five masters:
– Cortex®-M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
– Ethernet DMA
• Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB to APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:
Figure 2. System architecture in connectivity line devices
Co r t ex -M3
DMA1
ICode
DCode
FLITF
Sys tem
DMA
Reset & clock
control (RCC)
Flash
SRAM
Ch.1
Ch.2
Ch.7
DMA2
Ch.1
Ch.2
Ch.5
AHB system bus
Bridge 2
Bridge 1
APB2
APB 1
DMA request
ADC1
ADC2
USART1
SPI1
TIM1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
EXTI
AFIO
DAC SPI3/I2S
PWR SPI2/I2S
BKP IWDG
CAN1 WWDG
CAN2 RTC
I2C2
TIM7
I2C1
TIM6
UART5 TIM5
UART4 TIM4
USART3 TIM3
USART2 TIM2
DMA request
Ethernet MAC
USB OTG FS
ai15810
ICode bus
This bus connects the Instruction bus of the Cortex®-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
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