P80C54SBAA View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
P80C54SBAA Datasheet PDF : 56 Pages
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Philips Semiconductors
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Product specification
8XC54/58
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7V to +5.5V, VSS = 0V1, 2, 3
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/tCLCL
FIGURE
29
PARAMETER
Oscillator frequency5
Speed versions : 4; 5;S
MIN MAX
MIN
3.5
MAX
16
UNIT
MHz
tLHLL
29
tAVLL
29
tLLAX
29
tLLIV
29
tLLPL
29
tPLPH
29
tPLIV
29
tPXIX
29
tPXIZ
29
tAVIV 5
29
tPLAZ
29
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
85
2tCLCL–40
ns
22
tCLCL–40
ns
32
tCLCL–30
ns
150
4tCLCL–100
ns
32
tCLCL–30
ns
142
3tCLCL–45
ns
82
3tCLCL–105
ns
0
0
ns
37
tCLCL–25
ns
207
5tCLCL–105
ns
10
10
ns
tRLRH
30, 31
tWLWH
30, 31
tRLDV
30, 31
tRHDX
30, 31
tRHDZ
30, 31
tLLDV
30, 31
tAVDV
30, 31
tLLWL
30, 31
tAVWL
30, 31
tQVWX
30, 31
tWHQX
30, 31
tQVWH
31
tRLAZ
30, 31
tWHLH
30, 31
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
275
6tCLCL–100
ns
275
6tCLCL–100
ns
147
5tCLCL–165
ns
0
0
ns
65
2tCLCL–60
ns
350
8tCLCL–150
ns
397
9tCLCL–165
ns
137 239
3tCLCL–50
3tCLCL+50
ns
122
4tCLCL–130
ns
13
tCLCL–50
ns
13
tCLCL–50
ns
287
7tCLCL–150
ns
0
0
ns
23
103
tCLCL–40
tCLCL+40
ns
tCHCX
33
tCLCX
33
tCLCH
33
tCHCL
33
Shift Register
High time
Low time
Rise time
Fall time
20
20
tCLCL–tCLCX
ns
20
20
tCLCL–tCHCX
ns
20
20
ns
20
20
ns
tXLXL
32
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
32
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
32
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
32
Input data hold after clock rising edge
0
0
ns
tXHDV
32
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.
2000 Aug 07
38
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