ST90E40L0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST90E40L0 Datasheet PDF : 56 Pages
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ST90E40 - ST90T40
GENERAL DESCRIPTION (Continued)
Three basic memory spaces are available to sup-
port this wide range of configurations: Program
Memory (internal and external),Data Memory (ex-
ternal) and the Register File, which includes the
control and status registers of the on-chip peripher-
als.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other sys-
temmsiming functions by the usage of the two
associated DMA channels for each timer.
In addition there is an 8 channel Analog to Digital
Converter with integral sample and hold, fast 11µs
conversion time and 8 bit resolution. An Analog
Watchdog feature is included for two input chan-
nels.
Completing the device is a full duplex Serial Com-
munications Interface with an integral 110 to
375,000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully program-
mable format) and associated address/wake-up
option, plus two DMA channels.
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (R/W), and
Data Memory signals are valid for program or data
memory transfers. Under program control, AS can
be placed in a high-impedance state along with
Port 0 and Port 1, Data Strobe (DS) and R/W.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a write
cycle, data out is valid at the leading edge of DS.
During a readcycle, DataIn must be valid prior to the
trailing edge of DS. When the ST9040 accesseson-
chipmemory, DS is held high duringthe wholemem-
ory cycle. It can be placed in a high impedancestate
along with Port 0, Port 1, AS andR/W.
R/W. Read/Write (output, 3-state). Read/Write de-
termines the direction of data transfer for external
memorytransactions.R/W is low when writing to ex-
ternal program or data memory,and high for all other
transactions. It can be placed in a high impedance
state along with Port 0, Port 1, AS and DS.
RESET/VPP. Reset (input, active low) or VPP (in-
put). The ST9 is initialised by the Reset signal.
With the deactivation of RESET, program execu-
tion begins from the Program memory location
pointed to by the vector contained in program
memory locations 00h and 01h. In the EPROM
programming Mode, this pin acts as the program-
ming voltage input VPP.
iNT0, INT7. Externalinterrupts (input, active on ris-
ing or falling edge). External interrupt inputs 0 and
7 respectively. INT0 channel may also be used for
the timer watchdog interrupt.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the in-
put of the oscillator inverter and internal clock gen-
erator; OSCOUT is the output of the oscillator
inverter.
AVDD. Analog VDD of the Analog to Digital Con-
verter.
AVSS. Analog VSS of the Analog to Digital Con-
verter. Must be tied to VSS.
VDD. Main Power Supply Voltage (5V ± 10%)
VSS. Digital Circuit Ground.
P0.0-P0.7, P1.0-P1.7, P2.0-P2.7 P3.0-P3.7, P4.0-
P4.7, P5.0-P5.7, P7.0-P7.7 I/O Port Lines (In-
put/Output, TTL or CMOS compatible). 56 lines
grouped into I/O ports of 8 bits, bit programmable
under program control as general purpose I/O or
as alternate functions.
1.2.1 I/O PORT ALTERNATE FUNCTIONS
Each pin of the I/O ports of the ST90E40/T36 may
assume software programmable Alternative Func-
tions as shown in the Pin Configuration Tables.
Due to Bonding options for the packages, some
functions may not be present, Table 3 shows the
Functions allocatedto each I/O Port pin and a sum-
mary of packages for which they are available.
39/56
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