ST90E40 - ST90T40
1.1 GENERAL DESCRIPTION
The ST90E40 and ST90T40 (following mentioned
as ST90E40)are EPROM members ofthe ST9 fam-
ilyof microcontrollers, in windowed ceramic (E) and
plastic OTP (T) packages respectively, completely
developed and produced by SGS-THOMSON Mi-
croelectronics using a n-well proprietary HCMOS
process.
The EPROM parts are fully compatible with their
ROM versions and this datasheet will thus provide
only information specific to the EPROM based de-
vices.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9040 ROM-BASED DE-
VICE FOR FURTHER DETAILS.
The EPROM ST90E40 may be used for the proto-
typing and pre-production phases of development,
and can be configured as: a standalone microcon-
troller with 16K bytes of on-chip EPROM, a micro-
controller able to manageexternal memory, or as a
parallel processing element in a system with other
processors and peripheral controllers.
The nucleus of the ST90E40 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface support-
ing S-bus, I2C-bus and IM-bus Interface,plus two 8
bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipe-
lining to add to the efficiency of the code execution
speed of the extensive instruction set.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the ST90E40
with up to 56 I/O lines dedicated to digital In-
put/Output. These lines are grouped into up to
seven 8 bit I/O Ports and can be configured on a bit
basis under software control to provide timing,
status signals, an address/data bus for interfacing
external memory, timer inputs and outputs, analog
inputs, external interrupts and serial or parallel I/O
with or without handshake.
Figure 3. ST90E40 Block Diagram
16k Bytes
E P RO M
512 Bytes
EEPROM
INT0 INT7
256 Bytes
RAM
256 Bytes
REGISTER FILE
1 6-Bit TIMER / WATCHDOG + SPI
CPU
SCI
WITH DMA
8
I/O PORT 7
( SCI )
MEMORY BUS
REGISTER BUS
I/O PORT 0
( Address/Data )
I/O PORT 1
( Address )
I/O PORT 2
( SPI )
I/O PORT 3
( TIMERS )
8
8
8
8
2 x 16-bit TIMER
W ITH DM A
I/O PORT 4
( Ana log Inpu ts )
8
A /D
CONVERTER
I/O PORT 5
WITH HANDSHAKE
AVD D AVS S
8
V R 0 A 1 3 85
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