Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

ST90E40G0 Ver la hoja de datos (PDF) - STMicroelectronics

Número de piezacomponentes DescripciónFabricante
ST90E40G0 16K ROM HCMOS MCU WITH EEPROM, RAM AND A/D CONVERTER ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST90E40G0 Datasheet PDF : 56 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ST9040
EXTERNAL BUS TIMING TABLE
(VDD = 5V ± 10%,TA = – 40 °C to + 85 °C, Cload = 50pF, CPUCLK = 12MHz, unless otherwise specified)
N°
Symbol
1 TsA (AS)
2 ThAS (A)
3 TdAS (DR)
4 TwAS
5 TdAz (DS)
6 TwDSR
7 TwDSW
8 TdDSR (DR)
9 ThDR (DS)
10 TdDS (A)
11 TdDS (AS)
12 TsR/W (AS)
13 TdDSR (R/W)
14 TdDW (DSW)
15 ThDS (DW)
16 TdA (DR)
17 TdAs (DS)
Parameter
OSCIN Divided
By 2
Value (Note)
OSCIN Not Divided
By 2
Unit
Min. Max.
Address Set-up Time
before AS
TpC (2P+1) –22
TWCH+PTpC –18 20
ns
Address Hold Time after AS TpC –17
TwCL –13
25
ns
AS to Data Available (read)
TpC (4P+2W+4) –52 TpC (2P+W+2) –51
115 ns
AS Low Pulse Width
TpC (2P+1) –7
TwCH+PTpC –3
35
ns
Address Float to DS t
12
12
12
ns
DS Low Pulse Width (read)
TpC (4P+2W+3) –20
TwCH+TpC
(2P+W+1) –16
105
ns
DS Low Pulse Width (write)
TpC (2P+2W+2) –13 TpC (P+W+1) –13 70
ns
DS toData Valid Delay (read)
TpC (4P+2W-3) –50
TwCH+TpC(2P+W+1)
–46
75 ns
Data to DS Hold Time (read) 0
0
0
ns
DS to Address Active Delay TpC –7
TwCL –3
35
ns
DS to AS Delay
TpC –18
TwCL –14
24
ns
R/W Set-up Time before AS TpC (2P+1) –22
TwCH+PTpC –18 20
ns
DS to R/W and Address Not
Valid Delay
TpC –9
TwCL –5
33
ns
Write Data Valid to DS Delay
(write)
TpC (2P+1) –32
TwCH+PTpC –28 10
ns
Data Hold Time after DS (write) TpC –9
TwCL –5
33
ns
Address Valid to Data Valid
Delay (read)
TpC (6P+2W+5) –68
TwCH+TpC
(3P+W+2) –64
140 ns
AS to DS Delay
TpC –18
TwCL –14
24
ns
EXTERNAL WAIT TIMING TABLE
(VDD = 5V ± 10%,TA = –40°C to +85°C, Cload = 50pF,
INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified)
N°
Symbol
Parameter
OSCIN Divided
By 2
Value (Note)
OSCIN Not Divided
Unit
Min. Max.
By 2
1 TdAs (WAIT) AS to WAIT Delay
2(P+1)TpC –29
2(P+1)TpC –29
40 ns
2 TdAs (WAIT) AS to WAIT Min. Delay
2(P+W+1)TpC –4 2(P+W+1)TpC –4 80
ns
3 TdAs (WAIT) AS to WAIT Max. Delay
2(P+W+1)TpC –29 2(P+W+1)TpC –29
83W+
40
ns
Note: (for both tables) The value in the left hand two columns show the formula used to calculate the timing minimum or maximum from the
oscillator clock period, prescale value and number of wait cycles inserted.
The value in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler value
of zero and zero wait status.
Legend:
TpC =OSCIN Period
P = Clock Prescaling Value
TwCH =High Level OSCIN half period
W = Wait Cycles
TwCL =Low Level OSCIN half period
17/56
®
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]