M1A3P400-2FG484YI View Datasheet(PDF) - Microsemi Corporation

Part Name

Description

Manufacturer

M1A3P400-2FG484YI

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Microsemi Corporation 

ProASIC3 DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to Advanced I/O Banks

3.3 V

Equiv.

LVCMOS Software

Wide Range Default

Drive

Drive

Strength

Strength

Option1

VIL

Min. Max.

V

V

VIH

Min. Max.

V

V

VOL

Max.

V

VOH IOL IOH IOSL

Min.

V

Max.

µA µA mA4

IOSH IIL2 IIH3

Max.

mA4 µA5 µA5

100 µA

2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25

27 10 10

100 µA

4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25

27 10 10

100 µA

6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51

54 10 10

100 µA

8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51

54 10 10

100 µA

12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 103

109 10 10

100 µA

16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 132

127 10 10

100 µA

24 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 268

181 10 10

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to Standard Plus I/O Banks

3.3 V LVCMOS

Wide Range

Drive Strength

Equiv.

Software

Default

Drive

Strength

Option1

VIL

VIH

VOL

Min. Max. Min. Max. Max.

V

VVV

V

VOH

Min.

V

IOL IOH IOSL IOSH IIL2 IIH3

Max. Max.

µA µA mA4 mA4 µA5 µA5

100 µA

2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25

27 10 10

100 µA

4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25

27 10 10

100 µA

6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51

54 10 10

100 µA

8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51

54 10 10

100 µA

12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 103 109 10 10

100 A

16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 103 109 10 10

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

4. Currents are measured at 85°C junction temperature.

5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

6. Software default selection highlighted in gray.

2-38

Revision 14

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