ISL88731A
Functional Pin Descriptions
BOOT
High-Side Power MOSFET Driver Power-Supply Connection.
Connect a 0.1µF capacitor from BOOT to PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the high-side
N-Channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to low-side
N-Channel MOSFET. LGATE drives between VDDP and PGND.
PHASE
High-Side Power MOSFET Driver Source Connection. Connect to
the source of the high-side N-Channel MOSFET.
CSOP
Charge Current-Sense Positive Input.
CSON
Charge Current-Sense Negative Input.
CSSP
Input Current-Sense Positive Input.
CSSN
Input Current-Sense Negative Input.
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to
GND.
ACIN
AC-adapter Detection Input. Connect to a resistor divider from the
AC-adapter output.
ACOK
AC Detect Output. This open drain output is high impedance
when ACIN is greater than 3.2V. The ACOK output remains low
when the ISL88731A is powered down. Connect a 10k pull-up
resistor from ACOK to VDDSMB.
ICM
Input Current Monitor Output. ICM voltage equals 20 x (VCSSP -
VCSSN).
VREF
VREF is a reference output pin. It is internally compensated. Do
not connect a decoupling capacitor.
PGND
Power Ground. Connect PGND to the source of the low side
MOSFET.
VCC
Power input for internal analog circuits. Connect a 4.7Ω resistor
from VCC to VDDP and a 1µF ceramic capacitor from VCC to
ground.
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V linear
regulator supplied from DCIN. VDDP also directly supplies the
LGATE driver and the BOOT strap diode. Bypass with a 1µF
ceramic capacitor from VDDP to PGND.
ICOMP
Compensation Point for the charging current and adapter current
regulation Loop. Connect 0.01µF to GND. See “Voltage Control
Loop” on page 20 for details of selecting the ICOMP capacitor.
VCOMP
Compensation Point for the voltage regulation loop. Connect
4.7kΩ in series with 0.01µF to GND. See “Voltage Control Loop”
on page 20 for details on selecting VCOMP components.
VFB
Feedback for the Battery Voltage.
VDDSMB
SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to GND.
SDA
SMBus Data I/O. Open-drain Output. Connect an external pull-up
resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
GND
Analog Ground. Connect directly to the backside paddle. Connect
to PGND close to the output capacitor.
Back Side Paddle
Connect the backside paddle to GND.
NC
No Connect. Pins 1, 5, 7 and 14 are not connected.
8
FN6738.3
June 8, 2011