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74VHCT125 Quad buffer/line driver; 3-state NXP
NXP Semiconductors. NXP
74VHCT125 Datasheet PDF : 15 Pages
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Nexperia
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Fig 8.
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Load circuit for switching times
Table 9. Test data
Type
Input
74VHC125
74VHCT125
VI
VCC
3.0 V
tr, tf
3.0 ns
3.0 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 k
1 k
S1 position
tPHL, tPLH
open
open
tPZH, tPHZ
GND
GND
tPZL, tPLZ
VCC
VCC
74VHC_VHCT125_2
Product data sheet
Rev. 02 — 13 October 2009
© Nexperia B.V. 2017. All rights reserved
9 of 15
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