74HC5555 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

74HC5555

Programmable delay timer with oscillator

NXP Semiconductors. 

Philips Semiconductors

Programmable delay timer with oscillator

Product specification

74HC/HCT5555

handbook, full pagewidth

1 RS

OSC

14 CON

2

R TC

3

10 11 12 13

C TC S0 S1 S2 S3

CP

24 - STAGE COUNTER

CD

POWER-ON

RESET

15 MR

4A

5B

6 RTR/RTR

MONOSTABLE

CIRCUITRY

OUTPUT

STAGE

Q9

Q7

Fig.3 Functional diagram.

MGA644

FUNCTIONAL DESCRIPTION

The oscillator configuration allows the

design of RC or crystal oscillator

circuits. The device can operate from

an external clock signal applied to the

RS input (RTC and CTC must not be

connected). The oscillator frequency

is determined by the external timing

components (RT and CT), within the

frequency range 1 Hz to 4 MHz

(32 kHz to 20 MHz with crystal

oscillator).

In the HCT version the MR input is

TTL compatible but the RS input has

CMOS input switching levels. The RS

input can be driven by TTL input

levels if RS is tied to VCC via a pull-up

resistor.

The counter divides the frequency to

obtain a long pulse duration. The

24-stage is digitally programmed via

the select inputs (S0 to S3). Pin S3 can

also be used to select the test mode,

which is a convenient way of

functionally testing the counter.

The “5555” is triggered on either the

positive-edge, negative-edge or both.

• Trigger pulse applied to input A for

positive-edge triggering

• Trigger pulse applied input B for

negative-edge triggering

• Trigger pulse applied to inputs A

and B (tied together) for both

positive-edge and negative

triggering.

The Schmitt trigger action in the

trigger inputs, transforms slowly

changing input signals into sharply

defined jitter-free output signals and

provides the circuit with excellent

noise immunity.

The OSC CON input is used to select

the oscillator mode, either

continuously running (OSC CON =

HIGH) or triggered start mode (OSC

CON = LOW). The continuously

running mode is selected where a

start-up delay is an undesirable

feature and the triggered start mode

is selected where very low power

consumption is the primary concern.

The start of the programmed time

delay occurs when output Q goes

HIGH (in the triggered start mode, the

previously disabled oscillator will

start-up). After the programmed time

delay, the flip-flop stages are reset

and the output returns to its original

state.

An internal power-on reset is used to

reset all flip-flop stages.

The output pulse can be terminated

by the asynchronous overriding

master reset (MR), this results in all

flip-flop stages being reset. The

output signal is capable of driving a

power transistor. The output time

delay is calculated using the following

formula (minimum time delay is

100 ns):

-1f-i × division ratio (s).

Once triggered, the output width may

be extended by retriggering the

gated, active HIGH-going input A or

the active LOW-going input B. By

repeating this process, the output

pulse period (Q = HIGH, Q = LOW)

can be made as long as desired. This

mode is selected by RTR/RTR =

HIGH. A LOW on RTR/RTR makes,

once triggered, the outputs (Q, Q)

independent of further transitions of

inputs A and B.

September 1993

4

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