M1A3P400-2FGG144ES View Datasheet(PDF) - Unspecified

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Description

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M1A3P400-2FGG144ES

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Unspecified 

ProASIC3 Flash Family FPGAs

The Actel ProASIC3 development software solutions, Libero® Integrated Design Environment (IDE) and Designer,

have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files

for applications requiring a unique serial number in each part. Another feature allows the inclusion of static

data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero

IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy

programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and

south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are

256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can

be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM

emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be

configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are

programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in

addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary

for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to

create larger configurations.

PLL and CCC

ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the

ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not

have a PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well

as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the

CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / fOUT_CCC)

(for PLL only)

Global Clocking

ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support

described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global

networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes).

The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.

Product Brief

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