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M1A3P400-2FGG144ES View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
M1A3P400-2FGG144ES 1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support Unspecified
Unspecified 
M1A3P400-2FGG144ES Datasheet PDF : 196 Pages
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ProASIC3 DC and Switching Characteristics
Table 2-17 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
DC I/O Standards
IIL
IIH
µA
µA
3.3 V LVTTL / 3.3 V LVCMOS
10
10
2.5 V LVCMOS
10
10
1.8 V LVCMOS
10
10
1.5 V LVCMOS
10
10
3.3 V PCI
10
10
3.3 V PCI-X
10
10
Notes:
1. Commercial range (0°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
Industrial2
IIL
IIH
µA
µA
15
15
15
15
15
15
15
15
15
15
15
15
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-18 • Summary of AC Measuring Points
Standard
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Measuring Trip Point (Vtrip)
1.4 V
1.2 V
0.90 V
0.75 V
0.285 * VCCI (RR)
0.615 * VCCI (FF)
0.285 * VCCI (RR)
0.615 * VCCI (FF)
Table 2-19 • I/O AC Parameter Definitions
Parameter
Parameter Definition
tDP
tPY
tDOUT
tEOUT
tDIN
tHZ
tZH
tLZ
tZL
tZHS
tZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
2-18
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