M1A3P400-2FGG144ES View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

M1A3P400-2FGG144ES

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Unspecified 

I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V,

and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and differential.

The I/Os are organized into banks, with two or four banks per device. The configuration of these banks

determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the implementation

of the following:

• Single-Data-Rate applications

• Double-Data-Rate applications—DDR LVDS, BLVDS, and M-LVDS I/Os for point-to-point communications

ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-LVDS

can support up to 20 loads.

1-10

Product Brief

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