18.2.45SDBDPUâStream Descriptor Buffer Descriptor List Pointer Upper Base
Address Register (IntelÂź High Definition Audio ControllerâD27:F0) ............ 750
19 SMBus Controller Registers (D31:F3) .................................................................... 751
19.1 PCI Configuration Registers (SMBusâD31:F3)..................................................... 751
19.1.1 VIDâVendor Identification Register (SMBusâD31:F3)............................... 751
19.1.2 DIDâDevice Identification Register (SMBusâD31:F3) ............................... 752
19.1.3 PCICMDâPCI Command Register (SMBusâD31:F3) .................................. 752
19.1.4 PCISTSâPCI Status Register (SMBusâD31:F3) ........................................ 753
19.1.5 RIDâRevision Identification Register (SMBusâD31:F3) ............................. 753
19.1.6 PIâProgramming Interface Register (SMBusâD31:F3) .............................. 754
19.1.7 SCCâSub Class Code Register (SMBusâD31:F3)...................................... 754
19.1.8 BCCâBase Class Code Register (SMBusâD31:F3) .................................... 754
19.1.9 SMBMBAR0âD31_F3_SMBus Memory Base Address 0 (SMBusâD31:F3) ..... 754
19.1.10SMBMBAR1âD31_F3_SMBus Memory Base Address 1 (SMBusâD31:F3) ..... 755
19.1.11SMB_BASEâSMBus Base Address Register (SMBusâD31:F3)..................... 755
19.1.12SVIDâSubsystem Vendor Identification Register (SMBusâD31:F2/F4) ........ 755
19.1.13SIDâSubsystem Identification Register (SMBusâD31:F2/F4)..................... 756
19.1.14INT_LNâInterrupt Line Register (SMBusâD31:F3) ................................... 756
19.1.15INT_PNâInterrupt Pin Register (SMBusâD31:F3)..................................... 756
19.1.16HOSTCâHost Configuration Register (SMBusâD31:F3) ............................. 757
19.2 SMBus I/O and Memory Mapped I/O Registers .................................................... 758
19.2.1 HST_STSâHost Status Register (SMBusâD31:F3).................................... 759
19.2.2 HST_CNTâHost Control Register (SMBusâD31:F3) .................................. 760
19.2.3 HST_CMDâHost Command Register (SMBusâD31:F3).............................. 762
19.2.4 XMIT_SLVAâTransmit Slave Address Register (SMBusâD31:F3) ................ 762
19.2.5 HST_D0âHost Data 0 Register (SMBusâD31:F3) ..................................... 762
19.2.6 HST_D1âHost Data 1 Register (SMBusâD31:F3) ..................................... 762
19.2.7 Host_BLOCK_DBâHost Block Data Byte Register (SMBusâD31:F3) ............ 763
19.2.8 PECâPacket Error Check (PEC) Register (SMBusâD31:F3) ........................ 763
19.2.9 RCV_SLVAâReceive Slave Address Register (SMBusâD31:F3) ................... 764
19.2.10SLV_DATAâReceive Slave Data Register (SMBusâD31:F3) ....................... 764
19.2.11AUX_STSâAuxiliary Status Register (SMBusâD31:F3) .............................. 764
19.2.12AUX_CTLâAuxiliary Control Register (SMBusâD31:F3) ............................. 765
19.2.13SMLINK_PIN_CTLâSMLink Pin Control Register (SMBusâD31:F3) .............. 765
19.2.14SMBus_PIN_CTLâSMBus Pin Control Register (SMBusâD31:F3)................. 766
19.2.15SLV_STSâSlave Status Register (SMBusâD31:F3) ................................... 766
19.2.16SLV_CMDâSlave Command Register (SMBusâD31:F3)............................. 767
19.2.17NOTIFY_DADDRâNotify Device Address Register (SMBusâD31:F3) ............ 767
19.2.18NOTIFY_DLOWâNotify Data Low Byte Register (SMBusâD31:F3) ............... 768
19.2.19NOTIFY_DHIGHâNotify Data High Byte Register (SMBusâD31:F3) ............. 768
20 PCI Express* Configuration Registers.................................................................... 769
20.1 PCI Express* Configuration Registers (PCI ExpressâD28:F0/F1/F2/F3/F4/F5) ......... 769
20.1.1 VIDâVendor Identification Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 772
20.1.2 DIDâDevice Identification Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 772
20.1.3 PCICMDâPCI Command Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 773
20.1.4 PCISTSâPCI Status Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 774
20.1.5 RIDâRevision Identification Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 775
20.1.6 PIâProgramming Interface Register
(PCI ExpressâD28:F0/F1/F2/F3/F4/F5)................................................... 775
IntelÂź I/O Controller Hub 9 (ICH9) Family Datasheet
27