25Q64BV View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

25Q64BV

64M-bit Serial Flash Memory with uniform 4KB sectors and Dual/Quad SPI

Winbond 

W25Q64BV

11. CONTROL AND STATUS REGISTERS

The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the

availability of the Flash memory array, if the device is write enabled or disabled, the state of write

protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the

devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by

the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and

in some cases the /WP pin.

11.1 STATUS REGISTER

11.1.1 BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a

Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this

time the device will ignore further instructions except for the Read Status Register and Erase Suspend

instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status

register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready

for further instructions.

11.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a

Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write

disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

11.1.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and

S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status

Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be

protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected.

11.1.4 Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the

Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.

The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction

depending on the state of the SRP0, SRP1 and WEL bits.

11.1.5 Sector/Block Protect (SEC)

The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB

Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown

in the Status Register Memory Protection table. The default setting is SEC=0.

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Publication Release Date: July 08, 2010

Revision E

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