CY2292 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY2292

Three-PLL General-Purpose EPROM Programmable Clock Generator

Cypress Semiconductor 

CY2292

Switching Characteristics, Commercial 5.0V (continued)

Parameter

Name

Description

t9A

Clock Jitter[14]

t9B

Clock Jitter[14]

Peak-to-peak period jitter (t9A max. – t9A

min.), % of clock period (fOUT < 4 MHz)

Peak-to-peak period jitter (t9B max. – t9B

min.)

t9C

Clock Jitter[14]

(4 MHz < fOUT < 16 MHz)

Peak-to-peak period jitter (16 MHz < fOUT <

50 MHz)

t9D

Clock Jitter[14]

Peak-to-peak period jitter (fOUT > 50 MHz)

t10A

Lock Time for CPLL

Lock Time from Power-up

t10B

Lock Time for UPLL and Lock Time from Power-up

SPLL

Slew Limits

CPU PLL Slew Limits CY2292

CY2292F

Min.

20

20

Typ.

<0.5

<0.7

<400

<250

<25

<0.25

Max.

1

1

500

350

50

1

100

90

Unit

%

ns

ps

ps

ms

ms

MHz

MHz

Switching Characteristics, Commercial 3.3V

Parameter

t1

t3

t4

t5

t6

t7

t8

t9A

t9B

t9C

t9D

t10A

t10B

Name

Output Period

Output Duty

Cycle[11]

Rise Time

Fall Time

Output Disable

Time

Output Enable

Time

Skew

CPUCLK Slew

Description

Clock output range, 3.3V CY2292

operation

CY2292F

Duty cycle for outputs, defined as t2 ÷ t1[12]

fOUT > 66 MHz

Duty cycle for outputs, defined as t2 ÷ t1[12]

fOUT < 66 MHz

Output clock rise time[13]

Output clock fall time[13]

Time for output to enter three-state mode after

SHUTDOWN/OE goes LOW

Time for output to leave three-state mode after

SHUTDOWN/OE goes HIGH

Skew delay between any identical or related

outputs[3, 12, 14]

Frequency transition rate

Min.

12.5

(80 MHz)

15

(66.6 MHz)

40%

Typ.

50%

45% 50%

3

2.5

10

10

< 0.25

1.0

Clock Jitter[14]

Clock Jitter[14]

Clock Jitter[14]

Clock Jitter[14]

Peak-to-peak period jitter (t9A max. – t9A min.),

% of clock period (fOUT < 4 MHz)

Peak-to-peak period jitter (t9B max. – t9B min.)

(4 MHz < fOUT < 16 MHz)

Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz)

Peak-to-peak period jitter (fOUT > 50 MHz)

Lock Time for CPLL Lock Time from Power-up

Lock Time for Lock Time from Power-up

UPLL and SPLL

Slew Limits

CPU PLL Slew Limits

CY2292

20

CY2292F

20

< 0.5

< 0.7

< 400

< 250

< 25

< 0.25

Max.

13000

(76.923 kHz)

13000

(76.923 kHz)

60%

55%

5

4

15

15

0.5

20.0

1

1

500

350

50

1

80

66.6

Unit

ns

ns

ns

ns

ns

ns

ns

MHz/

ms

%

ns

ps

ps

ms

ms

MHz

MHz

Document #: 38-07449 Rev. *C

Page 6 of 11

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