CY2292 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY2292

Three-PLL General-Purpose EPROM Programmable Clock Generator

Cypress Semiconductor 

Pin Configurations

CY2292

16-pin SOIC

CLKC 1

VDD 2

GND 3

XTALIN 4

XTALOUT 5

XBUF 6

CLKD 7

CPUCLK 8

16 SHUTDOWN/OE

15 S2/SUSPEND

14 VDD

13 S1

12 S0

11 GND

10 CLKA

9 CLKB

CY2292

Pin Summary

Name

CLKC

VDD

GND

XTALIN[1]

XTALOUT[1, 2]

XBUF

CLKD

CPUCLK

CLKB

CLKA

S0

S1

S2/SUSPEND

SHUTDOWN/OE

Pin Number

CY2292

Description

1

Configurable clock output C.

2, 14

Voltage supply.

3, 11

Ground.

4

Reference crystal input or external reference clock input.

5

Reference crystal feedback.

6

Buffered reference clock output.

7

Configurable clock output D.

8

CPU frequency clock output.

9

Configurable clock output B.

10

Configurable clock output A.

12

CPU clock select input, bit 0.

13

CPU clock select input, bit 1.

15

CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3]

16

Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only

places outputs in three-state[4] condition and does not shut down chip when LOW.

Operation

The CY2292 is a third-generation family of clock generators.

The CY2292 is upwardly compatible with the industry standard

ICD2023 and ICD2028 and continues their tradition by

providing a high level of customizable features to meet the

diverse clock generation needs of modern motherboards and

other synchronous systems.

All parts provide a highly configurable set of clocks for PC

motherboard applications. Each of the four configurable clock

outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in

any combination. Multiple outputs configured for the same or

related[3] frequencies will have low (≤ 500 ps) skew, in effect

providing on-chip buffering for heavily loaded signals.

The CY2292 can be configured for either 5V or 3.3V operation.

The internal ROM tables use EPROM technology, allowing full

customization of output frequencies. The reference oscillator

has been designed for 10-MHz to 25-MHz crystals, providing

additional flexibility. No external components are required with

this crystal. Alternatively, an external reference clock of

frequency between 1 MHz and 30 MHz can be used.

Output Configuration

The CY2292 has four independent frequency sources on-chip.

These are the reference oscillator, and three Phase-Locked

Loops (PLLs). Each PLL has a specific function. The System

PLL (SPLL) provides fixed output frequencies on the config-

urable outputs. The SPLL offers the most output frequency

divider options. The CPU PLL (CPLL) is controlled by the

select inputs (S0–S2) to provide eight user-selectable

frequencies with smooth slewing between frequencies. The

Utility PLL (UPLL) provides the most accurate clock. It is often

used for miscellaneous frequencies not provided by the other

frequency sources.

All configurations are EPROM programmable, providing short

sample and production lead times. Please refer to the appli-

cation note Understanding the CY2291, CY2292, and CY2295

for information on configuring the part.

Notes:

1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF.

2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).

3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.

4. The CY2292 has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.

Document #: 38-07449 Rev. *C

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