24C256(2012) View Datasheet(PDF) - ON Semiconductor
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24C256 Datasheet PDF : 18 Pages
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CAT24C256
Table 7. A.C. CHARACTERISTICS − Mature Product (Rev D) (Notes 10, 11)
(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, and VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Standard
Fast
Fast−Plus
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Symbol
Parameter
Min
Max
Min
Max
Min
Max
FSCL
Clock Frequency
100
400
1,000
tHD:STA
START Condition Hold Time
4
0.6
0.25
tLOW
Low Period of SCL Clock
4.7
1.3
0.55
tHIGH
High Period of SCL Clock
4
0.6
0.25
tSU:STA
START Condition Setup Time
4.7
0.6
0.25
tHD:DAT
Data In Hold Time
0
0
0
tSU:DAT
Data In Setup Time
250
100
50
tR (Note 12)
SDA and SCL Rise Time
1,000
300
100
tF (Note 12)
SDA and SCL Fall Time
300
300
100
tSU:STO
STOP Condition Setup Time
4
0.6
0.25
tBUF
Bus Free Time Between
4.7
1.3
0.5
STOP and START
tAA
SCL Low to Data Out Valid
3.5
0.9
0.50
tDH
Data Out Hold Time
100
100
50
Ti (Note 12)
Noise Pulse Filtered at SCL
100
100
100
and SDA Inputs
tSU:WP
WP Setup Time
0
0
0
tHD:WP
WP Hold Time
2.5
2.5
1
tWR
Write Cycle Time
5
5
5
tPU
Power-up to Ready Mode
1
1
0.1
1
(Notes 12, 13)
10. The product Rev D is identified by letter “D” or a dedicated marking code on top of the package.
11. Test conditions according to “A.C. Test Conditions” table.
12. Tested initially and after a design or process change that affects this parameter.
13. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 8. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x VCC to 0.8 x VCC
≤ 50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x VCC, 0.7 x VCC
0.5 x VCC
Current Source: IL = 3 mA (VCC ≥ 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
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