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NM93C46AVN データシートの表示(PDF) - National ->Texas Instruments

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NM93C46AVN 1024-Bit Serial EEPROM (MICROWIRE Bus Interface) National-Semiconductor
National ->Texas Instruments National-Semiconductor
NM93C46AVN Datasheet PDF : 12 Pages
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Functional Description
The NM93C46AL has seven instruction sets as described
below Note that the MSB of any instruction is a ‘‘1’’ and is
viewed as a start bit in the interface sequence The next 8 9
bits carry the op code and the 6 7-bit address for register
selection
All Data-in signals are clocked into the device on the low-to-
high SK transition
Read (READ)
The READ instruction outputs serial data on the DO pin
After a READ instruction is received the instruction and ad-
dress are decoded followed by data transfer from the se-
lected memory register into an 8- or 16-bit serial-out shift
register A dummy bit (logical 0) precedes the 8- or 16-bit
data output string Output data changes are intiated by a low
to high transition of the SK clock
Erase Write Enable (WEN)
When VCC is applied to the part it powers up in the Erase
Write Disable (WDS) state Therefore all programming
modes must be preceded by an WEN instruction Once an
Erase Write Enable instruction is executed programming
remains enabled until an Erase Write Disable (WDS) in-
struction is executed or VCC is removed from the part
Erase (ERASE)
This ERASE instruction will program all bits in the specified
register to the logical ‘‘1’’ state CS is brought low following
the loading of the last address bit This falling edge of the
CS pin initiates the self-timed programming cycle
The DO pin indicates the READY BUSY status of the chip if
CS is brought high after the tCS interval DO e logical ‘‘0’’
indicates that programming is still in progress DO e logical
‘‘1’’ indicates that the register at the address specified in
the instruction has been erased and the part is ready for
another instruction
Write (WRITE)
The WRITE instruction is followed by 8 bits or 16 bits of data
to be written into the specified address After the last bit of
data is put on the data-in (DI) pin CS must be brought low
before the next rising edge of the SK clock This falling edge
of CS initiates the self-timed programming cycle The DO
pin indicates the READY BUSY status of the chip if CS is
brought high after the tCS interval DO e logical 0 indicates
that programming is still in progress DO e logical 1 indi-
cates that the register at the address specified in the in-
struction has been written with the data pattern specified in
the instruction and the part is ready for another instruction
Erase All (ERAL)
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical ‘‘1’’
state The ERAL cycle is identical to the ERASE cycle ex-
cept for the different op-code As the ERASE mode the DO
pin indicates the READY BUSY status of the chip if CS is
brought high after the tCS interval The ERAL instruction is
not required see note below
Write All (WRALL)
The WRALL instruction will simultaneously program all reg-
isters with the data pattern specified in the instruction As in
the WRITE mode the DO pin indicates the READY BUSY
status
Erase Write Disable (WDS)
To protect against accidental data disturb the WDS instruc-
tion disables all programming modes and should follow all
programming operations Execution of a READ instruction is
independent of both the WEN and WDS instructions
Note The NM93C46AL device does not require an ‘‘ERASE’’ or ‘‘ERASE ALL’’ prior to the ‘‘WRITE’’ and ‘‘WRITE ALL’’ instructions The ‘‘ERASE’’ and ‘‘ERASE
ALL’’ instructions are included to maintain compatibility with the NMOS NMC9346
Instruction Set
Instruction Start Bit
READ
1
ERASE
1
WRITE
1
WEN
1
WDS
1
ERAL
1
WRALL
1
Opcode
1
0
1
1
0
1
0
0
0
0
0
0
0
0
Address
128 x 8
64 x 16
A6 – A0
A5 – A0
A6 – A0
A5 – A0
A6 – A0
A5 – A0
11XXXXX 11XXXX
00XXXXX 00XXXX
10XXXXX 10XXXX
01XXXXX 01XXXX
Data
128 x 8 64 x 16
D7 – D0 D15 – D0
D7 – D0 D15 – D0
Comments
Read Selected Address
Erase Selected Address
Write Selected Address
Program Enable
Program Disable
Erase All Addresses
Program All Addresses
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