DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

M48T128V-70PM1TR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
M48T128V-70PM1TR
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M48T128V-70PM1TR Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M48T128Y, M48T128V*
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
A0-A16
E
tAVEL
tAVWL
tAVAV
VALID
tAVWH
tWLWH
tWHAX
W
DQ0-DQ7
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHQX
AI02382
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
A0-A16
E
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
tEHAX
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02383
8/22
 

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]