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ST72141K View Datasheet(PDF) - STMicroelectronics

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ST72141K Datasheet PDF : 132 Pages
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ST72141K
RESET MANAGER (Cont’d)
External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor
(see Figure 11). This pull-up has no fixed value but
varies in accordance with the input voltage. It can
be pulled low by external circuitry to reset the de-
vice.
A RESET signal originating from an external
source must have a duration of at least tPULSE in
order to be recognized. Two RESET sequences
can be associated with this RESET source as
shown in Figure 12.
When the RESET is generated by a internal
source, during the two first phases of the RESET
sequence, the device RESET pin acts as an out-
put that is pulled low.
Generic Power On RESET
The function of the POR circuit consists of waking
up the MCU by detecting (at around 2V) a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the RESET state. When the power supply volt-
age rises to a sufficient level, the oscillator starts to
operate, whereupon an internal 4096 CPU cycles
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate-
ly following the internal delay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
cient level for the chosen frequency (see Electrical
Characteristics) before the reset signal is re-
leased. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy (os-
cillating) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performance.
Figure 12. External RESET Sequences
VDD nominal
VLVDf
VDD
RUN
t PUL SE
DELAY
RESET
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
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