Pin Function Description
20 thru 26
Open drain output to enable system PLL clock. It goes low 13 switching cycles after VCORE is within
10% of VBOOT.
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
A resistor to GND sets internal current reference. A 147kΩ resistor sets the controller for CPU core
application and a 47kΩ resistor sets the controller for GPU core application.
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
This pin is the inverting input of the error amplifier.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
ISUM- and Droop current sense input.
5V bias power.
Power stage supply voltage, used for feed-forward.
DPRSTP# A mode signal from the CPU. Combined with the DPRSLPVR signal, it determines the operational
mode of the controller.
Connect an MLCC capacitor across the BOOT and the PHASE pin. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT pin, each time the PHASE
pin drops below VCCP minus the voltage dropped across the internal boot diode.
Output of the high-side MOSFET gate driver. Connect the UGATE pin to the gate of the high-side
Current return path for the high-side MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor.
Current return path for the low-side MOSFET gate driver. Connect the VSSP pin to the source of the
low-side MOSFET through a low impedance path, preferably in parallel with the traces connecting
the LGATE pins to the gates of the low-side MOSFET.
Output of the low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the Phase-1
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to the VSSP pin.
VID0 thru VID input with VID0 = LSB and VID6 = MSB.
VR_ON Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode. It also programs the output voltage slew rate at 10mV/µs for
DPRSLPVR = 0 and 2.5mV/µs for DPRSLPVR = 1.
The bottom pad is electrically connected to the GND pin inside the IC. It should also be used as the
thermal pad for heat removal.
March 16, 2010