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62884CIRTZ Просмотр технического описания (PDF) - Intersil

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62884CIRTZ Single-Phase PWM Regulator for IMVP-6™ Mobile CPUs Intersil
Intersil Intersil
62884CIRTZ Datasheet PDF : 30 Pages
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ISL62884C
Theory of Operation
Multiphase R3™ Modulator
VW
MASTER CLOCK CIRCUIT
MASTER COMP
CLOCK VCRM
CLOCK
GMVO
CRM
SLAVE CIRCUIT
VW
CLOCK SQ PWM
L
R
PHASE
IL
VCRS
GM
CRS
VO
CO
FIGURE 3. R3™ MODULATOR CIRCUIT
VW
VCRM
COMP
CLOCK
PWM
VCRS
VW
HYSTERETIC
W IND O W
FIGURE 4. R3™ MODULATOR OPERATION PRINCIPLES
IN STEADY STATE
VW
VCRM
COMP
CLOCK
PWM
VW
The ISL62884C is a single-phase regulator implementing
Intel® IMVP-6™ protocol. It uses Intersil patented
R3™(Robust Ripple Regulator™) modulator. The R3
modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 3 conceptually shows the
ISL62884C R3™ modulator circuit, and Figure 4 shows
the operation principles.
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
the two pins. This voltage window is called VW window in
the following discussion.
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuit. The
modulator discharges the ripple capacitor Crm with a
current source equal to gmVo, where gm is a gain factor.
Crm voltage Vcrm is a sawtooth waveform traversing
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot clock
signal.
The slave circuit has its own ripple capacitor Crs, whose
voltage mimics the inductor ripple current. A gm
amplifier converts the inductor voltage into a current
source to charge and discharge Crs. The slave circuit
turns on its PWM pulse upon receiving the clock signal,
and the current source charges Crs. When Crs voltage
Vcrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
Since the ISL62884C works with Vcrs, which is
large-amplitude and noise-free synthesized signal, the
ISL62884C achieves lower phase jitter than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL62884C
has an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
Figure 5 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the clock signal more quickly, so the
PWM pulse turns on earlier, increasing the effective
switching frequency, which allows for higher control loop
bandwidth than conventional fixed frequency PWM
controllers. The VW voltage rises as the COMP voltage
rises, making the PWM pulse wider. During load release
response, the COMP voltage falls. It takes the master
clock circuit longer to generate the next clock signal so
the PWM pulse is held off until needed. The VW voltage
falls as the VW voltage falls, reducing the current PWM
pulse width. This kind of behavior gives the ISL62884C
excellent response speed.
VCRS
FIGURE 5. R3™ MODULATOR OPERATION PRINCIPLES
IN LOAD INSERTION RESPONSE
11
FN7591.0
March 16, 2010
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