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M4-32/32-7JC View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
M4-32/32-7JC High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns Lattice
Lattice Semiconductor Lattice
M4-32/32-7JC Datasheet PDF : 62 Pages
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Table 4. MACH 4A Speed Grades
Speed Grade1, 2
Device
-5
-55
-6
-65
-7
-10
-12
-14
M4A3-32
M4A5-32
C
C
C
C
C, I
C, I
C, I
I
M4A3-64
M4A5-64
C
C
C
C
C, I
C, I
C, I
I
M4A3-96
M4A5-96
C
C
C
C
C, I
C, I
C, I
I
M4A3-128
C
C
C
C
C, I
C, I
C, I
I
M4A5-128
M4A3-192
C
C
C
C
C, I
C, I
C, I
I
M4A5-192
M4A3-256
C
C
C
C
C, I
C, I
C, I
I
M4A5-256
C
C
C, I
C, I
I
M4A3-384
C
C
C, I
C, I
I
M4A3-512
C
C
C, I
C, I
I
Notes:
1. C = Commercial, I = Industrial
2. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on
availability.
The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), and fine-
pitch BGA (fpBGA) packages ranging from 44 to 352 pins (Tables 5 and 6). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-
V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/
Os, a programmable power-down mode for extra power savings and individual output slew rate
control for the highest speed transition or for the lowest noise transition.
Table 5. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)
Package
M4-32/32 M4-64/32 M4-96/48 M4-128/64 M4-128N/64 M4-192/96 M4-256/128
M4LV-32/32 M4LV-64/32 M4LV-96/48 M4LV-128/64 M4LV-128N/64 M4LV-192/96 M4LV-256/128
44-pin PLCC
32+2
32+2
44-pin TQFP
32+2
32+2
48-pin TQFP
32+2
32+2
84-pin PLCC
64+6
100-pin TQFP
48+8
64+6
100-pin PQFP
64+6
144-pin TQFP
96+16
208-pin PQFP
128+14
256-ball BGA
128+14
MACH 4 Family
5
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