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M4-128 View Datasheet(PDF) - Lattice Semiconductor

Part NameDescriptionManufacturer
M4-128 High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns Lattice
Lattice Semiconductor Lattice
M4-128 Datasheet PDF : 62 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input Register Delays with ZHT Option:
tSIRZ
Input register setup time -
ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
tHIRZ
Input register hold time -
ZHT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
Input Latch Delays with ZHT Option:
tSILZ
Input latch setup time -
ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
tHILZ Input latch hold time - ZHT 0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
tPDILZi
Transparent input latch to
internal feedback - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0 ns
Output Delays:
tBUF Output buffer delay
1.5
1.5
2.0
2.0
2.5
3.0
3.0
3.0 ns
tSLW Slow slew rate delay adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5 ns
tEA Output enable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0 ns
tER Output disable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0 ns
Power Delay:
tPL
Power-down mode delay
adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5 ns
Reset and Preset Delays:
Asynchronous reset or
tSRi preset to internal register
output
7.5
7.7
8.0
8.0
9.5
11.0
13.0
16.0 ns
tSR
Asynchronous reset or
preset to register output
9.0
9.2
10.0
10.0
12.0
14.0
16.0
19.0 ns
Asynchronous reset and
tSRR preset register recovery 7.0
7.0
7.5
7.5
8.0
8.0
10.0
15.0
ns
time
tSRW
Asynchronous reset or
preset width
7.0
7.0
8.0
8.0
10.0
10.0
12.0
15.0
ns
Clock/LE Width:
tWLS Global clock width low
2.0
2.0
2.5
2.5
3.0
5.0
6.0
6.0
ns
tWHS Global clock width high 2.0
2.0
2.5
2.5
3.0
5.0
6.0
6.0
ns
Product term clock width
tWLA low
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
Product term clock width
tWHA high
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
Global gate width low (for
tGWS low transparent) or high 4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
(for high transparent)
Product term gate width
tGWA
low (for low transparent)
or high (for high
4.0
4.0
4.5
4.5
5.0
5.0
6.0
9.0
ns
transparent)
tWIRL
Input register clock width
low
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
44
MACH 4 Family
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