M4-128 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
M4-128
Lattice Semiconductor
M4-128 Datasheet PDF : 62 Pages
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Frequency:
External feedback, D-type, Min of 1/(tWLS + tWHS) or 90.9
80.0
66.7
50.0
50.0
41.7
MHz
1/(tSS + tCOS)
External feedback, T-type, Min of 1/(tWLS + tWHS) or 83.3
74.1
62.5
47.6
47.6
40.0
MHz
1/(tSST + tCOS)
fMAXS
Internal feedback (fCNT), D-type,
Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi)
111.1
95.2
76.9
55.6
55.6
45.5
MHz
Internal feedback (fCNT), T-type,
Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi)
100.0
87.0
71.4
52.6
52.6
43.5
MHz
No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or
1/(tSST + tHS)
153.8
100.0
83.3
83.3
83.3
71.4
MHz
External feedback, D-type, Min of 1/(tWLA + tWHA) or 76.9
62.5
52.6
38.5
38.5
33.3
MHz
1/(tSA + tCOA)
External feedback, T-type, Min of 1/(tWLA + tWHA) or 71.4
58.8
50.0
37.0
37.0
32.3
MHz
1/(tSAT + tCOA)
fMAXA
Internal feedback (fCNTA), D-type,
Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi)
90.9
71.4
58.8
41.7
41.7
35.7
MHz
Internal feedback (fCNTA), T-type,
Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi)
No feedback2, Min of 1/(tWLA + tWHA),
1/(tSA + tHA) or 1/(tSAT + tHA)
83.3
66.7
55.6
40.0
40.0
34.5
MHz
125.0
100.0
62.5
55.6
55.6
50.0
MHz
fMAXI
Maximum input register frequency,
Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS)
111.0
100.0
83.3
83.3
83.3
71.4
MHz
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
Internal combinatorial
tPDi propagation delay
3.5
4.0
4.0
4.5
5.0
7.0
9.0
11.0 ns
tPD
Combinatorial propagation
delay
5.0
5.5
6.0
6.5
7.5
10.0
12.0
14.0 ns
Registered Delays:
Synchronous clock setup
tSS time, D-type register
3.0
3.5
4.0
4.0
5.5
6.0
7.0
10.0
ns
tSST
Synchronous clock setup
time, T-type register
4.0
4.0
4.5
4.5
6.5
7.0
8.0
11.0
ns
tSA
Asynchronous clock setup
time, D-type register
2.5
2.5
3.0
3.0
3.5
4.0
5.0
8.0
ns
tSAT
Asynchronous clock setup
time, T-type register
3.0
3.0
3.5
3.5
4.5
5.0
6.0
9.0
ns
tHS
Synchronous clock hold
time
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
MACH 4 Family
42
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