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U630H64BDC25G1 查看數據表(PDF) - Zentrum Mikroelektronik Dresden AG

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U630H64BDC25G1 HardStore 8K x 8 nvSRAM Zentrum
Zentrum Mikroelektronik Dresden AG Zentrum
U630H64BDC25G1 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU 10
STANDBY
tdis(E) (5)
tdis(G) (6)
Output Data Valid
tPD (11)
U630H64
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
25
35
45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
tAVAV
tAVAV
tcW 25
35
45
ns
tWLWH
tw(W) 20
30
35
ns
tWLEH tsu(W) 20
30
35
ns
tAVWL tAVEL
tsu(A)
0
0
0
ns
tAVWH tAVEH tsu(A-WH) 20
30
35
ns
tELWH
tsu(E) 20
30
35
ns
tELEH
tw(E)
20
30
35
ns
tDVWH tDVEH tsu(D) 12
18
20
ns
tWHDX tEHDX
th(D)
0
0
0
ns
tWHAX tEHAX
th(A)
0
0
0
ns
tWLQZ
tdis(W)
10
13
15 ns
tWHQX
ten(W)
5
5
5
ns
April 7, 2005
5
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