108296138 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

108296138

AmbassadorTM T8100A, T8102, and T8105 H.100/H.110 Interface and Time-Slot Interchangers

Agere -> LSI Corporation 

Ambassador T8100A, T8102, and T8105

H.100/H.110 Interfaces and Time-Slot Interchangers

Advance Data Sheet

November 1999

1 Product Overview (continued)

1.4 Ambassador TSI Architecture

The Ambassador programmable TSIs have been

designed to meet today’s switching requirements. The

T8100A and T8105 TSIs have a hierarchical switching

capability. They can switch between the local input bus

and the local output bus. They also switch between the

H.100/H.110 bus and local bus. The T8102 TSI

switches between the H.100/H.110 bus and the local

bus.

All three TSIs have circuitry for subrate switching and

can interface to other computer telephony standards

such as MVIP, SC-Bus, and MC-1*.

1.5 Selecting Between T8105, T8102,

T8100A, and T8100

Features

Subrate

switching

Local-to-local

connections

Local-to-H.100

connections

CT_NETREFs

T8100 T8100A

—

1,024

√

1,024

256

256

1

2

T8102 T8105

√

√

— 1,024

512 512

2

2

1.6 Enhanced Local Stream Addressing

Local stream addressing has 1024 locations. Separate

connection and data memories (T8100A, T8105 only)

maintain all necessary information for local stream

interconnections. The streams may operate at maxi-

mum rate on eight physical inputs and eight physical

outputs. Choices for slower input or output rates

allow enabling of additional physical inputs or outputs

for a maximum of 16 pins each. Data rates are

2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.

In addition to the enhanced serial streaming, the local

memories may be used for 8-line-serial-in/1-byte-paral-

lel-out, 1-byte-parallel-in/8-line-serial-out, or 1-byte-

parallel-in/1-byte-parallel-out options. All three data

rates are supported in the parallel modes. The

addresses for the local memories (T8100A, T8105

only) have been simplified so that stream and time-slot

designations are automatically translated to the appro-

priate memory address, regardless of rate or serial/par-

allel modes.

1.7 Full H.100 Stream Address Support

The devices provide access to the full 4096 H.100 bus

slots (32 streams x 128 slots) or any standard subset

(H-MVIP has a maximum 24 streams x 128 time

slots, for example). The number of stored time-slot

addresses is limited to 512 (T8102, T8105 only) at any

one time, but these may be updated on the fly. In addi-

tion, accesses to and from the H.100 bus can be

directed through the 1024 local stream/time slots, giv-

ing a total space of 5120 time slots. Data rates are pro-

grammable on each of the 32 physical streams,

selected in groups of four. The rates are 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s.

1.8 Onboard PLLs and Clock Monitors

The devices use rate multipliers and state machines to

generate onboard frequencies for supporting the

H.100, H-MVIP, MVIP, MC-1, and SC-Buses. Pins are

provided for coupling the internal clock circuitry with

commonly available clock adapters and jitter attenua-

tors. If external resources are not available, an internal

digital phase-locked loop (DPLL) can be used to gener-

ate all the bus frequencies and remain synchronized to

an 8 kHz reference. One of several clock input refer-

ence sources may be selected, and separate input-

active detection logic can identify the loss of the individ-

ual input references. The entire clocking structure oper-

ates from a 16.384 MHz crystal or external input.

1.9 Phase Alignment of Referenced and

Generated Frames

If this resource is selected, special control logic will cre-

ate bit-sliding in the data streams when the reference

frame and generated frame are out of phase. The bit-

sliding refers to removing a fraction of a bit time per

frame until the frames are in phase.

* MC-1 is a multichassis communication standard based on MVIP.

The devices support this standard.

12

Lucent Technologies Inc.

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