Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
1 Product Overview (continued)
1.3 Pin Information (continued)
Table 4. Pin Descriptions: Microprocessor Interface Pins
Symbol
Pin Ball Type
Name/Description
RESET
24 J1 I Master Reset (Active-Low). See Section 3.1 Resets. 50 kΩ internal pull-
up.
A[1:0] 31—30 L4, I Microprocessor Interface, Address Lines. Internal 20 kΩ pull-down.
L2
D[7:0]
22—15 H1, I/O Microprocessor Interface, Data Lines. 8 mA drive, 50 kΩ internal pull-up.
H2,
G1,
H3,
G2,
F1,
G4,
G3
ALE
29 L1 I Address Latch Enable. Internal 20 kΩ pull-down.
CS
28 K3 I Chip Select (Active-Low). 50 kΩ internal pull-up.
RD (DS)
27 K2 I Read Strobe (Intel Mode [Active-Low]), Data Strobe (Motorola [Active-
Low]). 50 kΩ internal pull-up.
WR (R/W)
26 K1 I Write Strobe (Intel [Active-Low]), Read/Write Select (Motorola [Active-
Low]). 50 kΩ internal pull-up.
RDY (DTACK) 25
J3 O Data Ready (Intel), Data Transfer (Motorola [Active-Low]).
8 mA, open drain (user should add pull-up to this line).
Table 5. Pin Descriptions: JTAG Pins
Symbol
TCLK
TMS
TDI
TDO
TRST
Pin
Ball
9
E3
8
F4
7
D2
6
C1
5
E4
Type
I
I
I
O
I
Name/Description
JTAG Clock Input.
JTAG Mode Select. 50 kΩ internal pull-up.
JTAG Data Input. 50 kΩ internal pull-up.
JTAG Data Output. 8 mA drive, 3-state.
JTAG Reset (Active-Low). 50 kΩ internal pull-up.
10
Lucent Technologies Inc.