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SLX24C08/16 View Datasheet(PDF) - Siemens AG

Part NameDescriptionManufacturer
SLX24C08/16 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Siemens
Siemens AG Siemens
SLX24C08/16 Datasheet PDF : 22 Pages
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SLx 24C08/16
6
Read Operations
Reading of the EEPROM data is initiated by the Master with the command byte CSR.
6.1 Random Read
Random read operations allow the master to access any memory location.
Address Setting
Transmission of CSR
Transmission of
EEPROM Data
STOP Condition from
Master
The master generates a START condition followed by the
command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low on the SDA line.
Now the master transmits the EEPROM address (EEA) to the
EEPROM and the internal address counter is loaded with the
desired address.
After the acknowledge for the EEPROM address is received,
the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
S
S
T
T
S
Bus Activity A Command Byte EEPROM Address A Command Byte
T
Master
R
CSW
EEA n
R
CSR
O
T
T
P
SDA Line S
0
S
1
P
Bus Activity
EEPROM
A
A
C
C
K
K
A Data Byte
C
K
IED02133
Figure 11
Random Read
Semiconductor Group
15
1998-07-27
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