NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
16
RDSon
(mΩ)
Tj = 25 °C
12
8
4
VGS = 3.5 V
03af13
4V
4.5 V
5V
10 V
0
0
20
40
60
80
ID (A)
03af18
2
a
1.5
1
0.5
0
-60
0
60
120
180
Tj (°C)
Fig 9. Drain-source on-state resistance as a function Fig 10. Normalized drain-source on-state resistance
of gate-source voltage; typical values
factor as a function of junction temperature
10
VGS
(V)
8
ID = 50 A
Tj = 25 °C
VDD = 15 V
6
4
03af17
104
C
(pF)
103
03af16
Ciss
Coss
2
Crss
0
0
20
40
60
QG (nC)
102
10−1
1
10
102
VDS (V)
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHD96NQ03LT_6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
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